1. Field of the Invention
The invention relates to a semiconductor device that has an IGBT (Insulated Gate Bipolar Transistor) formed on an SOI (Silicon on Insulator) substrate divided by trenches and a method of manufacturing the same.
2. Description of the Related Art
A semiconductor device having an IGBT 54, control and drive circuits 55 for the IGBT 54, and so on formed on an SOI substrate divided by trenches 101,102,103 will be described referring to FIG. 10. A P− type semiconductor substrate 51 on which an IGBT 54, a control circuit 55 and so on are formed and isolated by dielectric isolation layers 56, 57, 58 is attached to a P− type semiconductor substrate 53 that is a supporting substrate and insulated from the P− type semiconductor substrate 51 by an embedded insulation film 52.
On the bottom portion of the P− type semiconductor substrate 51 adjacent to the embedded insulation film 52, a P+ type embedded emitter layer 59a is formed in the region for the IGBT 54 and a P+ type embedded layer 59b is formed in the region for the control circuit 55 and so on. A P+ type emitter layer 60 is formed in the region for the IGBT 54, being connected to the P+ type embedded layer 59a and extending along the sidewalls of the dielectric isolation layers 56, 57 to the front surface of the P− type semiconductor substrate 51 to be connected to the emitter electrode E1.
The IGBT 54 includes the emitter electrode E1 connected to an N+ type emitter layer 62, a P type base layer 63 and the P+ type emitter layer 60, a collector electrode C1 connected to a P+ type collector layer 64, an N type drift layer 65 and an N− type drift layer 66 that surround the P+ type collector layer 64, and a gate electrode G that extends from on the N− type drift layer 66 onto the N+ type emitter layer 62 with a gate insulation film 67 being interposed therebetween.
Although the control circuit 55 includes various device elements, an NPN bipolar transistor and a PNP bipolar transistor are representatively shown. The NPN bipolar transistor includes an emitter electrode E2 connected to an N+ type emitter layer 68 formed on the P− type semiconductor substrate 51 on the P+ type embedded layer 59b, a base electrode B2 connected to a P type base layer 69 surrounding the N+ type emitter layer 68, an N type collector layer 70 surrounding the P type base layer 69, and a collector electrode C2 connected to an N+ type embedded layer 71.
The PNP bipolar transistor includes an emitter electrode E3 connected to a P type emitter layer 72, a collector electrode C3 connected to a P type collector layer 73, a base electrode B3 connected to an N+ type embedded layer 74 surrounding the N type base layer 75. In this case, the N+ type embedded layer 71 and so on of the NPN bipolar transistor is formed in an inner region of the P− type semiconductor substrate 51 at about several μm from the front surface.
In the IGBT 54 in this figure, the emitter region is formed adjacent to the dielectric isolation layers 56, 57, and the collector region is formed in the center portion of the SOI island between the dielectric isolation layers 56, 57. In this structure, a collector current flows in the horizontal direction, and thus the channel density is low. Therefore, a structure of flowing a collector current in the vertical direction is employed by forming a plurality of emitter regions in the center of the SOI island so as to increase the channel density and by forming the collector region adjacent to the dielectric isolation layer.
In this case, the P+ type embedded emitter layer is replaced by a P+ type embedded collector layer, and the impurity concentration of the P+ type embedded collector layer need be high as much as possible so as to decrease the on-resistance. By replacing the P− type semiconductor substrate in the SOI island by an N− type semiconductor substrate, the N− type semiconductor substrate serves as an N type drift layer.
Such a semiconductor device having an IGBT and control and drive circuits for the IGBT foamed on an SOI substrate divided by trenches is disclosed in the Japanese Patent Application Publication No. Hei 7-45699.
The IGBT described above as having the emitter regions in the center portion of the island of the SOI substrate and having the collector region adjacent to the dielectric isolation layer 56 and so on, that is a modification of the IGBT described in the Japanese Patent Application Publication No. Hei 7-45699, is provided with a structure in which the impurity concentration of the P+ type embedded collector layer is increased so as to decrease the on-resistance as described above.
This contributes to increase in the dose of holes injected into the N type drift layer from the P+ type embedded collector layer when the IGBT is in the on state and thus decrease in the on-resistance of the low concentration N type drift layer, having an advantage in the so-called conductivity modulation effect. However, on the contrary, this has a problem of increasing the time until the recombination and extinction of excess injected holes are completed when the IGBT turns off, thereby causing degradation in the turn-off characteristic.
Furthermore, in order to form a high breakdown voltage IGBT, it is preferable to use a Floating zone (FZ) wafer of which the concentration of impurities such as oxygen is low as the P-type semiconductor substrate. However, since the diameters of semiconductor wafers are becoming larger, a Czochralski (CZ) wafer need be used instead of a FZ wafer having difficulty in increasing the diameter. This causes a problem in increasing the breakdown voltage and decreasing the leakage current.
Furthermore, the embedded collector layer and so on of the NPN bipolar transistor forming the control circuit or a P type low concentration embedded layer of a high breakdown voltage junction FET used for a level shifter in the P− type semiconductor substrate 51 need be formed in an inner region of the P− type semiconductor substrate 51 at about several μm from the front surface thereof. This need an ion implantation machine that applies a high current and high acceleration energy, and it is necessary to avoid crystal defects when ion implantation is performed. It is also necessary to address problems caused by using this P− type semiconductor substrate 51.
In the case of a high breakdown voltage IGBT, since the thickness of the SOI layer is thick, it is necessary to form deep trenches in the SOI layer. When the trench is deep, the thickness of a polysilicon filling the trench also becomes large and a recess portion is formed in the polysilicon on the trench. When a device element such as IGBT is formed on such a P− type semiconductor substrate, there is a problem that a planarization treatment need be performed on the polysilicon film.
Accordingly, the degradation of the turn-off characteristic, the problems caused by using the P− type semiconductor substrate 51, and the problems caused by forming the thick polysilicon film covering the trenches, as described above, need be addressed.